The present invention relates to a system for supplying power to a volatile semiconductor memory having a memory array, with an input voltage being present at a second connection of the semiconductor memory.
Semiconductor memories are divided into two groups: volatile and non-volatile memories. Volatile memories (temporary memories) can be read and written any number of times and are therefore known, for example, as random access memories (RAM). The information that they contain is lost when the supply voltage is cut off. Non-volatile memories (permanent memories) retain their information contents even after the supply voltage has been cut off and are also known as read-only memories.
A volatile semiconductor memory is part, for example, of a microcomputer. A program that can be processed by the microcomputer is stored in the memory array of the semiconductor memory. If the microcomputer is part of a controller for a motor vehicle, for example as part of an engine controller, the information contained in the memory array must remain permanently stored even after the motor vehicle has been turned off. For this purpose, the semiconductor memory is provided with a supply voltage that is permanently present at the semiconductor memory, i.e., particularly even when the motor vehicle is turned off.
The permanent voltage for permanent storage of the information contained in the memory array is supplied, in particular, from the vehicle battery and causes the vehicle battery to discharge slowly, due to quiescent current consumption. In addition, the current consumption of the semiconductor memory during the continuously supplied quiescent phase differs by multiple powers of ten from the current consumption during normal operation, when read and write access takes place. A complex system having two circuit segments having different drive capacities for quiescent mode and normal mode is therefore usually provided to supply power to the semiconductor memory. Switching between the two circuit segments occurs as needed. To minimize quiescent current consumption, the circuit segment having the high drive capacity for normal operation must be deactivated when the motor vehicle is at a standstill, since the vehicle battery would otherwise be quickly drained. In conventional designs, the circuit segment having the low drive capacity for the quiescent phase is nevertheless so complex that it consumes quiescent current at levels of, for example, several hundred microamperes.
The circuit segment having the low drive capacity must stabilize the input voltage, i.e., standby voltage, of the semiconductor memory to prevent fluctuations, particularly a decrease, in the supply voltage of the memory array from resetting the semiconductor memory, thus causing a complete loss of the information stored in the memory array. In addition, the circuit segment having the low drive capacity should protect the memory array against overvoltage pulses to avoid damaging the memory array, which would cause information to be lost.
An object of the present invention is to provide a system for supplying power to a semiconductor memory as simply and with as few components as possible, thereby minimizing quiescent current consumption in the system.
According to the present invention, this object may be achieved on the basis of the power supply system by providing the semiconductor memory with a stabilization circuit for stabilizing the input voltage, i.e., standby voltage, that has a low impedance when the input voltage (V_STBY) is elevated and a high impedance when the input voltage (V_STBY) is too low to supply power to the semiconductor memory (1, 1a).
In particular, this may be achieved according to the present invention by using a parallel circuit of a diode and a transistor, with the diode being connected by its anode to the input voltage, i.e., standby voltage, and by its cathode to a reference potential that is present at a third connection of the semiconductor memory; and with the transistor being connected by its junction, i.e., the drain/source channel in the case of a field-effect transistor (FET) or the emitter-collector junction in the case of a bipolar transistor, between the standby voltage and the reference potential, and the base of the transistor, i.e., the gate in the case of a field-effect transistor (FET) or the base in the case of a bipolar transistor, being connected to the input, i.e., standby, voltage. The terms input voltage and standby voltage are used interchangeably in the discussion below.
The system according to the present invention has a stabilization circuit of an especially simple design.
According to an example embodiment, the system includes only a diode and a transistor, which are connected to each other in a manner suitable for optimum stabilization of the standby voltage. The stabilization circuit in the system according to the present invention is integrated into the semiconductor memory. The system according to the present invention makes use of the fact that the stability of the standby voltage needs to meet only relatively minor requirements to ensure that the information remains stored in the memory array.
Other implementations of the stabilization circuit include use of a Zener diode, a voltage-dependent conductivity controller of a CMOS transistor or a temperature-compensated, voltage-dependent conductivity controller.
Because the stabilization circuit has a simple structure and a small number of components, an especially low working current may be selected for stabilizing the supply voltage during the semiconductor memory quiescent phase, which makes it possible to minimize quiescent current consumption. As a result, an especially small amount of current is drawn from the vehicle battery during the semiconductor memory quiescent phase, thus protecting the battery.
The diode of the stabilization circuit may be designed as a Zener diode. The transistor of the stabilization circuit may be designed as a FET, in particular a MOSFET. The transistor may be designed as an n-channel field-effect transistor.
According to an embodiment of the present invention, the second connection of the semiconductor memory can be connected to a supply voltage source via a resistor. The supply voltage source is designed, for example, as a car battery. A portion of the supply voltage decreases over the resistor, and the standby voltage is present at the second connection of the semiconductor memory. In the system according to the present invention, a resistor having a particularly high impedance may be selected, since the stabilization circuit requires only a very low working current to stabilize the standby voltage.
To smooth the standby voltage and bridge short-term dips in the supply voltage, the second connection of the semiconductor memory may be connected to the reference potential via a capacitor.
The semiconductor memory may include a protective circuit that has multiple series-connected clamping elements and is arranged between the standby voltage and the reference potential according to a further embodiment of the present invention. This protective circuit helps protect the memory array against overvoltage pulses. The clamping voltage of the protective circuit may be set by selecting a suitable number of clamping elements.
The clamping elements are advantageously designed as transistors that are series-connected to each other via the drain/source channel, with the gate of each transistor being connected to either the drain or the source of its own transistor. The transistors of the protective circuit may be designed as MOSFETs. The transistors of the protective circuit may be designed as n-channel field-effect transistors.